NDLI: Implementation of in-loop filter for HEVC decoder on reconfigurable processor

Content Provider	IET Digital Library
Author	Liu, Leibo Chen, Yingjie Deng, Chenchen Yin, Shouyi Wei, Shaojun
Abstract	The in-loop filter comprises deblocking filter and sample adaptive offset filter, which is an important module for improving image quality in a high-efficiency video coding (HEVC) decoder. The in-loop filter has a high computational complexity that accounts for ∼20% of the HEVC decoding computing load. Furthermore, it is difficult to implement a high-performing in-loop filter due to its large conditional processing requirement. First, this study presents a novel reconfigurable HEVC in-loop filter implementation on a coarse-grained dynamically reconfigurable processing unit. Next, a repartition scheme is presented that allows the in-loop filter implementation at a coding tree unit along with the other decoding modules in the HEVC decoder, which satisfies requirements of low latency applications. Finally, a hierarchised-pipeline and synchronised-parallel technique is used to improve performance by eliminating data hazards in pipeline techniques and synchronisation problems in parallel techniques. Implementation results show that the presented HEVC in-loop filter performs up to 1920 × 1080@52 frames per second at 250 MHz. The throughput is 67.5 × 9 × more than solutions based on digital signal processor and general-purpose processor, respectively.
Starting Page	685
Ending Page	692
Page Count	8
ISSN	17519659
Volume Number	11
e-ISSN	17519667
Issue Number	Issue 9, Sep (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/11/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2016.0143
Journal	IET Image Processing
Publisher Date	2017-05-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adaptive Filter Coarse-grained Dynamically Reconfigurable Processing Unit Computational Complexity Computer Vision And Image Processing Technique Conditional Processing Requirement Data Hazard Elimination Deblocking Filter Decoding Digital Signal Processor Frequency 250 MHz General-purpose Processor HEVC Decoder Hierarchised-pipeline Technique High-efficiency Video Coding Image And Video Coding Image Filtering Image Quality Reconfigurable HEVC In-loop Filter Reconfigurable Processor Repartition Scheme Sample Adaptive Offset Filter Synchronisation Synchronised-parallel Technique Video Coding Video Signal Processing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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