NDLI: XNORCONV: CNNs accelerator implemented on FPGA using a hybrid CNNs structure and an inter-layer pipeline method

Content Provider	IET Digital Library
Author	Zhang, Lin Bu, Xiaokang Li, Bing
Abstract	Nowadays, convolutional neural networks (CNNs) have become a research hotspot because of their high performance in computer vision and pattern recognition. However, as the high energy consumption of traditional graphic processing units-based CNNs, it is difficult to deploy them into portable devices. To deal with this problem, a hybrid CNN structure (XNORCONV) was proposed and implemented on field-programmable gate array (FPGA) in this study. Two improvements have been applied in XNORCONV. Firstly, the multiplications in the convolutional layer (CONV) were replaced by XNOR operations to save the multiplier and reduce computational complexity. Secondly, an inter-layer pipeline was designed to further accelerate the calculation. XNORCONV was implemented on Xilinx Zynq-7000 xc7z020clg400-1 under the clock frequency of 150 MHz and tested with MNIST dataset. The results of the experiment show that XNORCONV can classify each picture from MNIST in 18 .97 μ s , and achieve 98.4% recognition accuracy. Compared with traditional Lenet-5 on different platforms, XNORCONV reduced multiplication by 85.6% with only 0.4% accuracy loss.
Starting Page	105
Ending Page	113
Page Count	9
ISSN	17519659
Volume Number	14
e-ISSN	17519667
Issue Number	Issue 1, Jan (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/14/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2019.0385
Journal	IET Image Processing
Publisher Date	2019-10-08
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Circuit Implementations Clock Frequency CNNs Accelerator Computational Complexity Computer Vision Convolutional Layer Convolutional Neural Nets Convolutional Neural Network Digital Circuit Design, Modelling And Testing Energy Consumption Field Programmable Gate Array Field-programmable Gate Array FPGA Graphic Processing Units-based CNNs Hybrid CNNs Structure Inter-layer Pipeline Design Logic And Switching Circuit Logic Circuit Logic Design Method Logic Element Logic Gate MNIST Dataset Multiplier Multiplying Circuit Neural Chips Neural Net Device Neural Nets Pattern Recognition Pipeline Processing Xilinx Zynq-7000 Xc7z020clg400-1 XNOR Operation XNORCONV
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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