NDLI: Compact digital implementation of a non-coherent IR-UWB transmitter and receiver

Content Provider	IET Digital Library
Author	Hennessy, Andrew Alimohammad, Amirhossein
Abstract	Non-coherent impulse-radio ultra-wideband (IR-UWB) transceivers are attractive candidates for applications where the silicon area and power consumption are relatively limited. This study presents the compact digital architecture design and implementation of a non-coherent IR-UWB transmitter and receiver based on the energy detection scheme, including the synchroniser module. The software models of the designed transceiver are simulated and verified in both floating-point and fixed-point numerical representations. The synthesisable Verilog description of the transmitter and receiver architectures is simulated and verified against their fixed-point simulation model. The transmitter and receiver are implemented in the authors custom-developed field-programmable gate array (FPGA) board. The bit error rate performance of the transmitter and receiver is measured in real-time on the FPGA, utilising an accurate on-chip Gaussian noise generator. The characteristics and implementation results of the transmitter and receiver architecture on the FPGA are presented. An application-specific integrated circuit (ASIC) architecture of the IR-UWB transceiver is estimated to occupy 0.0227 mm2 and dissipate 760 mW from a 1.0 V supply while operating at 82 MHz in a standard 32 nm complementary metal–oxide–semiconductor technology.
Starting Page	2616
Ending Page	2622
Page Count	7
ISSN	17518628
Volume Number	12
e-ISSN	17518636
Issue Number	Issue 20, Dec (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-com/12/20
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-com.2018.5522
Journal	IET Communications
Publisher Date	2018-09-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application Specific Integrated Circuit CMOS Integrated Circuit Compact Digital Architecture Design Compact Digital Implementation Custom-developed Field-programmable Gate Array Board Error Statistics Field Programmable Gate Array Fixed-point Numerical Representations Fixed-point Simulation Model Frequency 82.0 MHz Hardware Description Languages Implementation Result Interpolation And Function Approximation IR-UWB Transceiver Noncoherent Impulse Radio Ultra Wideband Transceivers Noncoherent IR-UWB Transmitter Numerical Analysis Power 760.0 MW Radio Link And Equipment Radio Transceivers Signal Detection Size 32.0 Nm Statistics Ultra Wideband Communication Voltage 1 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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