NDLI: Reference voltage generation scheme enhancing speed and reliability for 1T1C-type FRAM

Content Provider	IET Digital Library
Author	Jia, Ze Zhang, Gong Liu, Jizhi Liu, Zhiwei Liou, Juin J.
Abstract	An improved reference voltage generation scheme is proposed for a 1T1C-type ferroelectric random access memory (FRAM), in which the circuit referring to reference cells is redefined and the data are written into reference cells at random between ‘1’ and ‘0’ depending on the voltages of the bitlines during every operation cycle. Compared with conventional schemes, it can not only realise higher access speed for memory, but also can enhance its reliability by resolving the imprint and relieving the fatigue relating to ferroelectric capacitors in the device. Functional verification for the experimental prototype utilising the proposed scheme has been implemented.
Starting Page	154
Ending Page	156
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 3, Jan (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2013.3193
Journal	Electronics Letters
Publisher Date	2014-01-17
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	1T1C-type Ferroelectric Random Access Memory 1T1C-type FRAM Capacitor Circuit Reliability Ferroelectric Capacitor Ferroelectric Device Ferroelectric Storage Memory Circuit Power Electronics Power Supply Random-access Storage Reference Circuit Reference Voltage Generation Scheme Reliability Semiconductor Storage Supervisory Circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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