NDLI: 0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

Content Provider	IET Digital Library
Author	Yan, Zushu Mak, Pui In Law, Man Kay Martins, Rui Paulo
Abstract	A three-stage amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-stage amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.
Starting Page	454
Ending Page	456
Page Count	3
ISSN	00135194
Volume Number	51
e-ISSN	1350911X
Issue Number	Issue 6, Mar (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/51/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.4391
Journal	Electronics Letters
Publisher Date	2015-03-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Active Parallel Compensation Amplifiers APC Area Efficiency Enhancement Capacitance 0.15 NF to 1.5 NF CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Three-stage Amplifier DC Gain Dominant Compensation Path ECMC Embedded Capacitor-multiplier Compensation Figure of Merit Frequency 1.13 MHz Large Gain-bandwidth Product Left-half-plane Zero Miller Effect NF-range Capacitive Load Passive Parallel Compensation Phase Margin PM Power 15.8 MuW Size 0.18 Mum Transconductance
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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