NDLI: Thermal synergies in 50 nanometer CMOS and below

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Thermal synergies in 50 nanometer CMOS and below

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Thermal synergies in 50 nanometer CMOS and below

Content Provider	IET Digital Library
Author	Shoucair, F. S.
Abstract	An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<±100 ppm/°C) and currents (<±400 ppm/°C) in standard complementary metal oxide semiconductor (CMOS) processes over wide temperature spans (–55°C to +163°C). The method involves combining devices with the same polarity (e.g. n‐channel MOSFETs in p‐well processes and vice versa) in a judicious manner suggested by theory, which side‐steps the need for disparate elements such as resistors, diodes, and bipolar transistors, whose thermal variations are more difficult to model and offset mutually; the more so, the wider the temperature range. The close agreement between analysis and simulations (BSIM4) is illustrated by representative circuit design examples embodying the proposed principles. The concepts set forth offer advantages as generally accrue from design simplification and reduced circuit complexity; they are scalable as industrial silicon CMOS processes – which are not optimised for extended thermal operation – evolve below 50 nm, and suitable to other technologies which find applications in the automotive, aviation, aerospace, energy, and geophysical sensing sectors, among others, such as silicon carbide, wherein MOSFETs can operate above 300°C. The author is indebted to Dr. John Khoury, Silicon Laboratories, Inc., Austin, TX, and to N. DiLauro for valuable technical discussions and assistance under the exceptional circumstances prevailing during 2020. The earlier assistance of Prof. S. Simic, Department of Mathematics and Statistics, San José State University, is gratefully acknowledged.
Starting Page	183
Ending Page	196
Page Count	14
Volume Number	15
e-ISSN	17518598
Issue Number	Issue 2, Mar (2021)
Alternate Webpage(s)	https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/cds2.12002
Alternate Webpage(s)	https://ietresearch.onlinelibrary.wiley.com/toc/17518598/2021/15/2
Journal	IET Circuits, Devices & Systems
Publisher Date	2021-02-10
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Content Type	Text
Resource Type	Article

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Single-Molecule FRET Detection of Sub-Nanometer Distance Changes in the Range below a 3-Nanometer Scale

CMOS integrated sensor circuit for temperature measurement based on 50 nm technology

The modified alpha power law based model of statistical fluctuation in nanometer FGMOSFET

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Advanced CMOS device technologies for 45 nm node and below

Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

Intrinsic and Systematic Variability in Nanometer CMOS Technologies

Thermal synergies in 50 nanometer CMOS and below

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