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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhenhui Lin Yingxi Zuo Qijun Yao |
| Copyright Year | 2004 |
| Description | Author affiliation: Purple Mountain Obs., Acad. Sinica, Nanjing, China (Zhenhui Lin; Yingxi Zuo; Qijun Yao) |
| Abstract | This paper presents a design of a 2-bit, 4-level digital correlator implemented with Xilinx Vertex-2 FPGAs. A technique of serial-to-parallel conversion of die input streams is adopted to reduce the speed requirement of the correlation circuits. The correlator can be used for auto- and cross-correlation, and is fully cascadable to form more lags with more FPGA chips. It can run at a clock of 250 MHz. and thus can manipulate input signals with bandwidth of 500 MHz thanks to the 1:4 serial-to-parallel converting scheme. |
| Starting Page | 375 |
| Ending Page | 377 |
| File Size | 153846 |
| Page Count | 3 |
| File Format | |
| ISBN | 0780384040 |
| DOI | 10.1109/APRASC.2004.1422488 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-08-24 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuits Signal sampling Bandwidth Signal processing Telescopes Frequency Correlators Timing Field programmable gate arrays Clocks |
| Content Type | Text |
| Resource Type | Article |
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