NDLI: High-performance transistor evaluation for low-cost embedded DRAM

Content Provider	IEEE Xplore Digital Library
Author	Furusawa, H. Nogami, S. Ogawa, T. Kumazaki, M. Okada, N. Yamamoto, H.
Copyright Year	2011
Description	Author affiliation: Technology Development Division, Micron Japan, Ltd., 302-2 Nishiwaki, Hyogo, 677-0063, Japan (Furusawa, H.; Nogami, S.; Ogawa, T.; Kumazaki, M.; Okada, N.; Yamamoto, H.)
Abstract	High-speed and low-power logic compatible performance is in high demanded for embedded DRAM (eDRAM) and/or custom DRAM applications. However, it is a challenge to make it cost-effectively using the commercial DRAM process. In this paper, the feasibility of high-performance transistors is demonstrated using the commercial Micron Technology 95nm DRAM process and design targeted for low-cost eDRAM. Multiple process conditions were optimized in the commercial DRAM process to simultaneously achieve the target performance and minimize DRAM retention time degradation. A dual-EPI process-thin selective EPI growth in the peripheral source/drain and thick selective EPI growth in the DRAM cell array-was experimentally developed to improve DRAM retention time. Parametrically, the dual-EPI process was successful, but further optimization is required for good yield.
Starting Page	1
Ending Page	4
File Size	262587
Page Count	4
File Format	PDF
ISBN	9781424497409
ISSN	19473834
e-ISBN	9781424497430
DOI	10.1109/WMED.2011.5767275
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	high speed Random access memory Implants MOSFET circuits Logic gates data retention time embedded DRAM low power DRAM Arrays Transistors
Content Type	Text
Resource Type	Article

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