NDLI: A multi-level DRAM with fast read and low power consumption

Content Provider	IEEE Xplore Digital Library
Author	Bo Liu Frenzel, J.F. Wells, R.B.
Copyright Year	2005
Description	Author affiliation: MRC Inst., Idaho Univ., Moscow, ID (Bo Liu; Frenzel, J.F.; Wells, R.B.)
Abstract	In this paper, we present a new, multi-level DRAM design, which can store 3 voltage levels (0, Vcc, and Vcc/2) in a single memory cell. This multi-level DRAM requires no special reference voltage and simplifies design of the peripheral circuits. Coding algorithms may be used to provide binary data immediately after first read, with the second read operation providing a second data word from the same cell; thus, binary data from two logical addresses can be obtained from one physical location. One of the coding algorithms uses an additional coding memory cell for every two data memory cells to provide 4-bits of binary data. A second algorithm uses 3 additional coding cells for every 8 data cells to provide 8-bit binary data for each access; thus every 11 memory cells can provide 16 bits of binary data. Furthermore, the read speed is faster than a conventional DRAM because the first access can complete before the word line reaches Vccp, and because a SRAM differential sense amplifier is used. Finally, storing 3 voltage levels in a single memory cell also reduces average power consumption, since the Vcc/2 voltage level requires less write back current than 0 or Vcc voltage level
Sponsorship	IEEE Electron Devices Soc. - Boise Chapter Electrochemistry Soc. ECS IEEE Boise Sect. IEEE EDS Region 6 / SRC Micron Found
Starting Page	59
Ending Page	62
File Size	1954589
Page Count	4
File Format	PDF
ISBN	0780390725
DOI	10.1109/WMED.2005.1431619
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Manufacturing industries Energy consumption Costs Flash memory Random access memory Voltage Production Differential amplifiers Circuit noise Noise level
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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