NDLI: Study of the performance of an optical packet switch architecture with highly distributed control in a data center environment

Content Provider	IEEE Xplore Digital Library
Author	Di Lucente, S. Pueyo Centelles, R. Dorren, H.J.S. Calabretta, N.
Copyright Year	2012
Description	Author affiliation: Eindhoven University of Technology, dept. Electrical Engineering, 5600MB, The Netherlands (Di Lucente, S.; Pueyo Centelles, R.; Dorren, H.J.S.; Calabretta, N.)
Abstract	We investigate the performance of an optical packet switch architecture with highly distributed control for interconnecting cluster switches in a data center environment. The optical packet switch under investigation can be scaled to a very large port count to interconnect a large number of cluster switches. Flow control is employed to regulate the packets transmission between the electronic buffers of the ingress and egress cluster switches. An important feature of the optical packet switch is that the switch can be re-configured in few nanoseconds regardless the port count. This is essential to minimize the end-to-end latency. Moreover, the limited contention resolution capability of the optical packet switch is compensated by the electronic buffers in the cluster switches. We numerically investigate the performance of an optical packet switch with 1024×1024 ports in terms of packet loss, throughput and latency in function of the electronic buffer capacity and number of retransmissions. Simulations results show that increasing the input buffer size allows for low packet loss at the expense of higher latency. On the contrary, limiting the number of retransmissions allows very low end-to-end latency but higher losses. For a system with 1024 in/out ports with a buffer size of 19 packets and a resend limit equal to 9, we obtain a packet loss lower than $10^{−3}$ and latency around 800 ns considering an input load of 0.5.
Starting Page	1
Ending Page	6
File Size	1379265
Page Count	6
File Format	PDF
ISBN	9781467314404
e-ISBN	9781467314428
e-ISBN	9781467314411
DOI	10.1109/ONDM.2012.6210266
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-17
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	optical packet switch architecture Limiting data center Optical switches distributed control Optical buffering Computer architecture Distributed control Throughput Optical packet switching
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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