NDLI: Design of a Design-for-Digital-Testability Third-Order S-? Modulator

Content Provider	IEEE Xplore Digital Library
Author	Shao-Feng Hung Hao-Chiao Hong
Copyright Year	2011
Abstract	This paper presents the design of a third-order Sigma-#Delta modulator with the design-for-digital-testability (DfDT) structure for audio applications. The DfDT structure not only makes the Sigma-#Delta modulator digitally testable but also provides many test benefits such as a low hardware overhead, high fault observability, high test accuracy, and the capability of conducting at-speed tests. The zero in the noise transfer function of the proposed third-order Sigma-#Delta modulator vanishes the shaped quantization noises near the passband. As a result, the shaped noise correction of the digital tests is less significant. It helps improve the test accuracy of the digital tests. The simulation results with the fully-settled linear behavior plus noise (FSLB+N) model show that the peak SNDR and the dynamic range of the proposed third-order Sigma-#Delta modulator using conventional analog stimuli are 86.8 dB and 90.6 dB respectively at an over-sampling ratio (OSR) of 64. The SNDR differences between analog tests and those of the corresponding digital tests are in-between 0.9 dB and -1.4 dB with an average of 0.06 dB when the Sigma-#Delta modulator is not overloaded. In addition, both kinds of tests have similar effective resolution bandwidth results (ERBW). The simulation results confirm that the proposed Sigma-#Delta modulator can have a low test cost and thus is suitable for SoC and built-in self-test (BIST) integrations thanks to the DfDT structure.
Starting Page	110
Ending Page	113
File Size	335321
Page Count	4
File Format	PDF
ISBN	9781457711442
e-ISBN	9780769544793
DOI	10.1109/IMS3TW.2011.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Simulation Noise Modulation Built-in self-test Dynamic range Design-for-Testability analog-to-digital converter Sigma-Delta modulator Passband Integrated circuit modeling
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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