NDLI: A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Khalili, F. Zarandi, H.R.
Copyright Year	2012
Abstract	This paper proposes a fault-tolerant multi-application mapping technique in NoC-based multiprocessor platforms. The proposed mapping technique is composed of two main parts: 1) Mapping an application core graph to a free non-faulty processing cores, 2) Placing spare cores among other free non-faulty processing cores. The former is a heuristic algorithm to map application core graph onto the platform to achieve higher performance and lower communication energy than previous techniques. The latter tunes the location of spare cores based on each application core graph, considering both transient and permanent core failures. With a good spare core placement, not only resource management is well performed, but also the failure containment is improved within the system. Many application core graphs generated by TGFF are used to evaluate the proposed technique. The simulations are performed using cycle-accurate Noxim simulator. The results of 1,000,000 fault injection experiments show that with confidence level of 95%, the proposed technique leads to communication energy reductions and performance improvement, compared to well-known related works.
Starting Page	421
Ending Page	428
File Size	1387170
Page Count	8
File Format	PDF
ISBN	9781467351652
e-ISBN	9780769549149
DOI	10.1109/ICCSE.2012.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-05
Publisher Place	Cyprus
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Energy consumption Application Mapping Tiles Heuristic algorithms Fault tolerant systems Task Migration Failure Recovery Scheduling Dynamic Spare Placement Circuit faults Fault-Tolerant
Content Type	Text
Resource Type	Article

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