NDLI: A folded pipeline network processor architecture for 100 Gbit/s networks

Content Provider	IEEE Xplore Digital Library
Author	Karras, K. Wild, T. Herkersdorf, A.
Copyright Year	2010
Description	Author affiliation: Tech. Univ. Muenchen, Muenchen, Germany (Karras, K.; Wild, T.; Herkersdorf, A.)
Abstract	Ethernet, although initially conceived as a Local Area Network technology, has been steadily making inroads into access and core networks. This has led to a need for higher link speeds, which are now reaching 100 Gbit/s. Packet processing at this rate represents a significant challenge, that needs to be met efficiently, while minimizing power consumption and chip area. This level of throughput favours a pipelined approach, thus this paper takes a traditional pipeline and breaks it down to mini-pipelines, which can perform coarse-grained processing (like process an MPLS label to completion). These mini-pipelines are then parallelized and used to construct a folded pipeline architecture, which augments the traditional approach by significantly reducing power consumption, a key problem in future routers. The paper compares the two approaches, discusses their advantages and disadvantages and demonstrates by quantitative measures that the folded pipeline architecture is the better solution for 100 Gbit/s processing.
Starting Page	1
Ending Page	11
File Size	1430785
Page Count	11
File Format	PDF
ISBN	9781424491278
e-ISBN	9781450303798
DOI	10.1145/1872007.1872010
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Content Type	Text
Resource Type	Article

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