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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Deng Pan Yuanyuan Yang |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Comput. Sci., State Univ. of New York Stony Brook, Stony Brook, NY (Deng Pan; Yuanyuan Yang) |
| Abstract | Traditional iterative matching algorithms for VOQ switches need three steps, i.e., request, grant and accept. By incorporating arbitration into the request step, two step iterative matching can be achieved. This enables simpler implementation and shorter scheduling time, while maintaining almost identical performance. As an example of the two step iterative matching algorithms, in this paper we present two step parallel iterative matching (PIM2), and theoretically prove that its average convergence iterations are less than In N + e/(e - 1) for an N X N switch. Furthermore, two step iterative matching algorithms can be efficiently pipelined on CIOQ switches so that two matchings can be obtained in each time slot. We propose a scheme called second of line (SOL) matching to provide two independent virtual switches, with which the pipelining can be achieved without additional scheduling time and arbitration hardware. More importantly, the pipelined algorithms are theoretically guaranteed to achieve 100% throughput for any admissible traffic. Extensive simulations are conducted to show that our analytical result on the average convergence iterations In N + e/(e - 1) is more accurate than the classical result $log_{2}$ N + 4/3, and to test the performance of different pipelined algorithms on CIOQ switches. |
| Starting Page | 41 |
| Ending Page | 50 |
| File Size | 220308 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781595930828 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-10-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Algorithm design and analysis convergence Switches Throughput Convergence Pipeline processing pipeline Analytical models Traffic control scheduling Iterative algorithms Hardware Performance analysis iterative algorithms |
| Content Type | Text |
| Resource Type | Article |
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