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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wang, L. Li, H. Song, C. Zhang, W. |
| Copyright Year | 2014 |
| Description | Author affiliation: Nat. Centre for Adv. Packaging (NCAP CHINA) Co. Ltd., Wuxi, China (Wang, L.; Li, H.; Song, C.; Zhang, W.) |
| Abstract | Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency $^{[1-3]}.$ Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the $HNO_{3}/HF/CH_{3}COOH(HNA)$ solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 1013333 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781479940264 |
| DOI | 10.1109/ESTC.2014.6962838 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-09-16 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Process control Silicon Etching Surface topography Through-silicon vias |
| Content Type | Text |
| Resource Type | Article |
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