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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nahill, B. Zilic, Z. |
| Copyright Year | 2015 |
| Description | Author affiliation: Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA, USA (Nahill, B.) || Integrated Microsyst. Lab., McGill Univ., Montreal, QC, Canada (Zilic, Z.) |
| Abstract | Non-volatile storage is an important element for many low-power wearable sensor platforms for data aggregation, audit logs, and to enable offline analytics and debugging. NAND flash is an increasingly appealing choice due to its low cost, low power consumption, and small footprint; but it requires high software complexity and overhead to use effectively in such resource-constrained environments. Many wearable processing systems have limited program memory and RAM, on the order of kilobytes, however current NAND flash file systems require 10s of kilobytes of code and RAM to provide rudimentary logging facilities to SD cards or flash memories. By constraining access patterns to practical cases for logging and optimizing operations around the timing needs of real-time systems, we can do better. This paper presents the design and evaluation of a NAND flash logging file system, available freely under a permissive license, in only a few kilobytes of ROM and a few hundred bytes of RAM. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 1074594 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467372015 |
| DOI | 10.1109/BSN.2015.7299353 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Ash Logic gates Real-time systems Timing Error correction codes Resource management |
| Content Type | Text |
| Resource Type | Article |
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