NDLI: Buffer control in H.264/AVC applications by implementing dynamic complexity-rate-distortion analysis

Content Provider	IEEE Xplore Digital Library
Author	Grois, D. Kaminsky, E. Hadar, O.
Copyright Year	2009
Description	Author affiliation: Electrical and Computer Engineering Department, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel (Kaminsky, E.) \|\| Communication Systems Engineering Department, Ben-Gurion University of the Negev, Beer-Sheva 84105, Israel (Grois, D.; Hadar, O.)
Abstract	In this work we present a novel optimal buffer control approach for H.264/AVC low-delay applications by dynamically allocating computational complexity (such as a number of CPU clocks) and bits for encoding each coding element (basic unit) within a video sequence, according to its predicted MAD (Mean Absolute Difference), while considering buffer size limitations (preventing underflow/overflow of the buffer) and buffer delay. Our buffer control approach is based on a computational complexity-rate-distortion (C-R-D) analysis, which adds a complexity dimension to the conventional rate-distortion (R-D) analysis. Both theoretically and experimentally, we prove that by implementing the proposed buffer control approach better results are achieved. In addition, we present an optimal buffer control method and system for implementing the proposed approach, and for controlling computational complexity and bit allocation in real-time and off-line video coding. We divide each frame into one or more basic units, wherein each basic unit consists of at least one macroblock (MB), whose contents are related to a number of coding modes. We determine how much computational complexity and bits should be allocated for encoding each basic unit, while considering buffer size limitations and buffer delay, and then we allocate a corresponding group of coding modes and a quantization step-size, according to the estimated distortion (calculated by a linear regression model) of each basic unit and according to the remaining computational complexity and bits for encoding remaining basic units. For allocating a corresponding group of coding modes and the quantization step-size, we develop computational complexity - complexity step - rate (C-I-R) and rate - quantization step-size - computational complexity (R-Q-C) models.
Starting Page	1
Ending Page	7
File Size	432077
Page Count	7
File Format	PDF
ISBN	9781424425907
DOI	10.1109/ISBMSB.2009.5133845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-13
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Video sequences Delay estimation Quantization Control systems Encoding H.264/AVC Computational complexity bit allocation video compression Optimal control computational complexity allocation Automatic voltage control rate control Size control buffer control Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamic Computational Complexity and Bit Allocation for Optimizing H.264/AVC Video Compression

Bit Allocation Scheme for Low-Delay H.264/AVC Rate Control

Complexity scalable rate-distortion optimization for H.264/AVC

Rate controlling based on effective source-complexity metrics appropriated to H.264/AVC

An efficient fast mode decision algorithm for H.264/AVC intra/inter predictions

Perceptually-friendly H.264/AVC video coding

Complexity Scalable H.264/AVC Encoding

A Fast Rate-Distortion Optimization Algorithm for H.264/AVC

A novel square root rate control algorithm for H.264/AVC encoding

Buffer control in H.264/AVC applications by implementing dynamic complexity-rate-distortion analysis

Similar Documents

Dynamic Computational Complexity and Bit Allocation for Optimizing H.264/AVC Video Compression

Bit Allocation Scheme for Low-Delay H.264/AVC Rate Control

Complexity scalable rate-distortion optimization for H.264/AVC

Rate controlling based on effective source-complexity metrics appropriated to H.264/AVC

An efficient fast mode decision algorithm for H.264/AVC intra/inter predictions

Perceptually-friendly H.264/AVC video coding

Complexity Scalable H.264/AVC Encoding

A Fast Rate-Distortion Optimization Algorithm for H.264/AVC

A novel square root rate control algorithm for H.264/AVC encoding

Buffer control in H.264/AVC applications by implementing dynamic complexity-rate-distortion analysis