NDLI: Quantum simulations of electrostatics in Si cylindrical nanowire pinch-off nFETs and pFETs with a homogeneous channel including strain and arbitrary crystallographic orientations

Content Provider	IEEE Xplore Digital Library
Author	Pham, A.T. Sorée, B. Magnus, W. Jungemann, C. Meinerzhagen, B. Pourtois, G.
Copyright Year	2011
Description	Author affiliation: EIT4, Universita¨t der Bundeswehr Mu¨nchen, 85577 Neubiberg, Germany (Jungemann, C.) \|\| Physics modelling and simulation, IMEC, 3001 Leuven, Belgium (Pham, A.T.; Sorée, B.; Magnus, W.; Pourtois, G.) \|\| BST, TU Braunschweig, 38023 Braunschweig, Germany (Meinerzhagen, B.)
Abstract	Junctionless nanowire pinch-off FETs [1–3] are promising device structures for beyond CMOS technologies. The device is called ”junctionless” [3] because it contains a uniform doping level $(n^{+}$ $n^{+}$ $n^{+}$ for nFETs or $p^{+}$ $p^{+}$ $p^{+}$ for pFETs) within the whole device including source, drain, and channel, which is different from the non-uniform $n^{+}$ $pn^{+}$ (or $p^{+}$ $np^{+})$ doping profiles in conventional nMOSFETs (or pMOSFETs). Therefore, during the fabrication the doping profile in junctionless nanowire pinch-off FETs is easier to control than in the conventional MOSFET case, especially for sub-100 nm gate length devices [3]. In additions, junctionless pinch-off FETs operate similar to JFETs and inversion is not required. In order to turn off the device, a sufficiently large \|VGS\| is required to extend the depletion region until pinch-off occurs. This is the reason for the name ”pinch-off” FET. If the horizontal cross-section area of the nanowire is scaled, the doping level must be increased in order to keep the threshold voltage unchanged [1]. Due to the high doping levels (typically $10^{18}$ $cm^{−3}$ to 5 × $10^{19}$ $cm^{−3})$ the carriers are strongly influenced by ionized impurity scattering, and as a consequence, the channel effective mobility is low. Therefore, it is important to include stress/strain engineering in combination with non-standard crystallographic channel orientations to boost the transport performance of the junctionless nanowire pinch-off FET.
Starting Page	1
Ending Page	4
File Size	138435
Page Count	4
File Format	PDF
ISBN	9781457700903
e-ISBN	9781457700910
e-ISBN	9781457700897
DOI	10.1109/ULIS.2011.5757989
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	Ireland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Doping Logic gates Capacitance Silicon Stress FETs Strain
Content Type	Text
Resource Type	Article

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