NDLI: A fully-parallel information detection hardware system employing Content Addressable Memory

Content Provider	IEEE Xplore Digital Library
Author	Duc-Hung Le Sowa, M. Cong-Kha Pham Inoue, K.
Copyright Year	2012
Description	Author affiliation: Advanced Original Technologies, Chiba, Japan (Inoue, K.) \|\| The University of Electro-Communications, Tokyo, Japan (Duc-Hung Le; Sowa, M.; Cong-Kha Pham)
Abstract	A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of searching and matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-matched results concurrently. The system operates based on the CAMs for pattern matching in parallel manner to return multiple addresses of multi-matched results. Based on the parallel multi-matching operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-matched results 60ns are achieved at the operational frequency 50 Mhz. Thus increases the matching performance of the information detection system which uses this method as the core system.
Starting Page	447
Ending Page	452
File Size	804189
Page Count	6
File Format	PDF
ISBN	9781467324922
e-ISBN	9781467324939
DOI	10.1109/CCE.2012.6315948
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-01
Publisher Place	Vietnam
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Information Detection Hardware System Computer aided manufacturing multiple match FPGA Random access memory Content Addressable Memory Time frequency analysis Registers Dual-port RAM parallel operation Hardware Cyclones Field programmable gate arrays
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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