NDLI: Workload adaptive shared memory multicore processors with reconfigurable interconnects

Content Provider	IEEE Xplore Digital Library
Author	Akram, S. Kumar, R. Deming Chen
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, USA (Akram, S.; Kumar, R.; Deming Chen)
Abstract	Interconnection networks for multicore processors are designed in a generic way to serve a diversity of workloads. For multicore processors, there is a considerable opportunity to achieve an improvement in performance by implementing interconnects which adapt to different program phases and to a variety of workloads. This paper proposes one such interconnection network for medium-scale (up to 32 cores) shared memory multicore processors and the associated means at the software level to utilize it effectively. The proposed architecture uses clustering to divide the cores on the chip among many groups called clusters. Reconfigurable logic is inserted between clusters to support either isolation or different policies for communication among clusters. The experiments show that the isolation property of clusters can improve overall throughput of a multicore processor by as much as 60% for multiprogramming workloads consisting of two and four applications. The area-overhead of the additional logic is shown to be minimal.
Starting Page	7
Ending Page	14
File Size	284125
Page Count	8
File Format	PDF
ISBN	9781424449392
DOI	10.1109/SASP.2009.5226329
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Multicore processing Multiprocessor interconnection networks Network-on-a-chip Reconfigurable logic Bandwidth Computer architecture Traffic control Throughput Delay
Content Type	Text
Resource Type	Article

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