NDLI: A low-power wide-band 20GHz VCO in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Guang Zhu Shengxi Diao Fujiang Lin Guidotti, D.
Copyright Year	2012
Description	Author affiliation: Department of System Packaging Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China (Guidotti, D.) \|\| Department of Electronic Science and Technology, University of Science and Technology of China, Hefei, China (Guang Zhu; Shengxi Diao; Fujiang Lin)
Abstract	A 20GHz (centralized at 18.7GHz) voltage controlled oscillator (VCO) is implemented in standard 65nm CMOS technology. In the design process, several design optimizations including tail current source, cross-couples dimension and inductor selection, are done to achieve a good performance without additional area requirement. Through these techniques, the measured phase noise of −98dBc/Hz@1MHz achieved at 19.97 GHz and the figure of merit (FOM) is −176dBc/Hz. With the help of digital controlled switch array, tuning range is about 15%, from 17.36 to 20.15 GHz without much performance degradation. The total current is 4.6mA under the 1.3V supply voltage, including the buffer current consumption of 0.9mA. To our best knowledge, this is the minimum current consumption for VCO in this frequency band. The area of the core circuit is only 0.35 × $0.25mm^{2}.$
Starting Page	291
Ending Page	294
File Size	172657
Page Count	4
File Format	PDF
ISBN	9781467313025
e-ISBN	9781467313056
DOI	10.1109/GSMM.2012.6314057
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise 20 GHz VCO Voltage-controlled oscillators Capacitors wide band CMOS technology low power CMOS integrated circuits Tuning
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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