NDLI: Improved Design and Characterization Method for Very High Speed Bipolar Circuits

Content Provider	IEEE Xplore Digital Library
Author	Kasbari, A.-E. Ouslimani, A. Blayac, S. Konczykowska, A.
Copyright Year	2008
Abstract	An improved design method for high speed bipolar circuits is presented. It uses iso base-collector capacitance curves superposed to the duty cycles plots in the (Ic,Vce) plane. This new optimization way gives the optimum operating region for each transistor of a bipolar circuit to reach the best trade-off between the switching speed and the power consumption. Electrical design of emitter-coupled pair, which constitutes the basis of emitter-coupled logic (ECL) circuits, is detailed to explain the design method. Each part of the measurement set-up is characterized in time and frequency domains to improve the measurement method. These improvements have enabled the design and characterization of InP double-heterojunction-bipolar transistor master-slave D-type flip-flop circuits. 40 Gb/s measurement with more than 85% eye-diagram opening validates this method.
Starting Page	344
Ending Page	347
File Size	1000062
Page Count	4
File Format	PDF
ISBN	9781424418855
DOI	10.1109/GSMM.2008.4534641
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Design methodology Logic circuits Capacitance Time measurement Logic design Frequency measurement Bipolar transistor circuits Frequency domain analysis Switching circuits
Content Type	Text
Resource Type	Article

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