NDLI: CMOS time-to-digital converter with low PVT sensitivity 20.8ps resolution and −0.25∼0.22 LSB inaccuracy

Content Provider	IEEE Xplore Digital Library
Author	Poki Chen Kai-Ming Wang Chuan-Yuan Li Po-Yu Chen Juan-Shan Lai Cheng-Wei Liu
Copyright Year	2011
Description	Author affiliation: Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan (Poki Chen; Kai-Ming Wang; Chuan-Yuan Li; Po-Yu Chen; Juan-Shan Lai; Cheng-Wei Liu)
Abstract	A simple but accuracy-enhanced CMOS time-to-digital converter (TDC) based on pulse stretcher interpolators is presented. Without the need of modifying the conventional circuit, both inaccuracy and PVT (process, voltage and temperature) sensitivity are substantially reduced. The errors caused by charge injection and clock feedthrough are eliminated by precise device sizing. The accuracy of current and capacitor ratios for its pulse stretchers is ensured by two-dimensional common centroid layouts. Fabricated in a TSMC 0.35µm standard CMOS process, the time resolution can be realized as 20.8ps and the INL error is proven to be −0.25∼0.22LSB for 0∼20ns input range. Moreover, the measured resolution merely spreads over 20.25∼20.96ps for twenty packaged chips. All fabricated chips were tested to be full functional under - 40∼120°C temperature operation range and 2.6∼4.9V supply voltage range with about ten-fold improvement in temperature drift and supply voltage sensitivity from its predecessor's.
Starting Page	127
Ending Page	130
File Size	179053
Page Count	4
File Format	PDF
ISBN	9781612846316
e-ISBN	9781612846323
DOI	10.1109/ASID.2011.5967432
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	pulse stretcher PVT sensitivity Capacitors device sizing Time-to-digital converter Temperature measurement charge injection Accuracy Sensitivity Layout dual-slop CMOS integrated circuits clock feedthrough Clocks
Content Type	Text
Resource Type	Article

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