NDLI: Design of power scaleable MD AC in high performance pipelined ADC

Content Provider	IEEE Xplore Digital Library
Author	Fei Pei Honghui Deng Yongsheng Yin
Copyright Year	2010
Description	Author affiliation: Institute of VLSI Design, Hefei University of Technology, Hefei, China (Fei Pei; Honghui Deng; Yongsheng Yin)
Abstract	A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly modulated by setting modulations of bias in op amp with different combinations of current sources. Simulation results in a 0.18um CMOS process indicated that when programmed at 125MSPS, the signal can correctly set up in 2.1ns; MDAC exhibits a spurious free dynamic range (SFDR)of 73.1 dB and a signal-to-noise and distortion ratio(SNDR)of 60.23dB. It consumes 6.8mw when a 62MHz sine signal is fed $in.^{1}$
Starting Page	108
Ending Page	111
File Size	323154
Page Count	4
File Format	PDF
ISBN	9781424467310
e-ISBN	9781424467341
DOI	10.1109/ICASID.2010.5551522
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Operational amplifiers pipeline Modulation Bandwidth Switches bias Logic gates MDAC MOS devices power modulation
Content Type	Text
Resource Type	Article

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