NDLI: Embedded Architectural Design Using Protection Logics to Defend Attack of Buffer Overflow and Unauthorized Access of Code

Content Provider	IEEE Xplore Digital Library
Author	Yau, C.H. Tan, Y.Y. Fong, A.S. Mok, P.L.
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong (Yau, C.H.; Tan, Y.Y.; Fong, A.S.; Mok, P.L.)
Abstract	As security is always a major concern in most of the networked computer systems, embedded systems should provide security features to defend the attack and protect the confidential and sensitive data. Many Trojan Horses and viruses use the security holes of exception to trigger attack, such as buffer overflow attack. Although most embedded systems rely on the programmer, the compiler or the third-party security software to defend and protect the systems against the buffer overflow attack, these techniques could not completely maintain the overall system security. Using a secure programming language is another approach to protect the system, but this approach contains a large security hole that break the overall security. Therefore, this paper proposes a secure Java embedded processor architecture called jHISC with protection logic to protect the system naturally. This new processor realized the natural secure language features of Java in the core architecture to enhance the overall system security. It performs various rigid hardware bound checks and embedded access control checks to avoid the code bypassing. The current implementation phase is under version 4 with 4 KB instruction cache and 8 KB data cache is described by VHDL and implemented and verified in a Xilinx Virtex FPGA.
Starting Page	264
Ending Page	269
File Size	145248
Page Count	6
File Format	PDF
ISBN	9780769532424
DOI	10.1109/CIT.2008.Workshops.119
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-08
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Java Embedded computing Data security Embedded system Logic design Computer networks Invasive software Buffer overflow Protection Computer security
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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