NDLI: A novel 4-point discrete fourier transforms circuit based on product of Rademacher functions

Content Provider	IEEE Xplore Digital Library
Author	Zulfikar Walidainy, H.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng., Syiah Kuala Univ., Banda Aceh, Indonesia (Zulfikar; Walidainy, H.)
Abstract	This paper presents a new circuit design for implementing 4-point DFT algorithm based on product of Rademacher functions. The circuit has been derived from the similarity of how Fourier transforms and Walsh transforms are implemented. Walsh matrices contain numbers either +1 or -1 except for first row. Similarly, the 4-point DFT matrix contain numbers either positive or negative except for first row. This similarity has been taken into the case of how to implement the DFT circuit based on how Walsh transforms is generated. Since Walsh transforms is derived based on product of Rademacher functions, the proposed 4-point DFT circuit is designed according to product Rademacher functions. The circuit consist of negative circuit, multiplexers, accumulator (real and imaginary), buffers, and control circuit. The control circuit is designed to produce Rademacher functions for controlling and managing data flow. The 4-point DFT circuit has been successfully designed and implemented to FPGA platform. Among the selected chips, Artix 7 is the fastest one.
Starting Page	132
Ending Page	137
File Size	363489
Page Count	6
File Format	PDF
ISBN	9781467367783
ISSN	21556830
e-ISBN	9781467373197
DOI	10.1109/ICEEI.2015.7352483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-10
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Multiplexing DFT Walsh transforms Buffer storage Frequency-domain analysis Discrete Fourier transforms Walsh matrix Rademacher functions DFT matrix
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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