NDLI: Improving generation method for test pattern based on BDD learning

Content Provider	IEEE Xplore Digital Library
Author	Liu Xin
Copyright Year	2011
Description	Author affiliation: School of Electrical & Electronic Engineering, Hubei University of Technology, Wuhan 430068, China (Liu Xin)
Abstract	To improving the efficiency of test pattern generation for combinational circuits based on the Boolean satisfiability (SAT) method, a TRL-based (Total Reconvergence Line) BDD (binary decision diagram) learning heuristics is presented in this paper. This heuristics combine the respective strengths of BDD, SAT and circuit structure based methods to solve local signal correlations. It firstly makes an analysis of the circuit topological structure to gather the information about local signal correlation through BDD learning. The above learned information in the conjunctive normal form clauses is then used to restrict and focus the overall search space of SAT-based test pattern generation. The experimental results show the validity of this approach.
Starting Page	200
Ending Page	203
File Size	106700
Page Count	4
File Format	PDF
ISBN	9781424481583
e-ISBN	9781424481613
DOI	10.1109/ICEMI.2011.6037887
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Boolean functions Correlation Design automation boolean satisfiability (SAT) test pattern generation heuristic learning Automatic test pattern generation Data structures conjunctive normal form (CNF) Circuit faults binary decision diagram (BDD)
Content Type	Text
Resource Type	Article

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