NDLI: Silent Sharing: An Efficient Mechanism to Fast Sequential Program Execution on Chip Multicore Processor

Content Provider	IEEE Xplore Digital Library
Author	Liqiang He Yan Sun
Copyright Year	2009
Abstract	Chip Multicore processor provides new opportunity to fast sequential program performance with the available duplicated hardware resources in the cores. Most of existed sequential programs can benefit from a larger instruction window and a bigger L2 cache. In this paper, we propose a simple mechanism, Silent Sharing, to faster sequential program execution on a chip multicore processor. The basic idea is to send long latency instructions in the instruction window to the windows in other cores, as well as evicted blocks from local L2 to the free blocks in remote L2s in order to get a relative bigger instruction window and L2 storage. All the transfer operations are not viewable by the running program. In other words, a running core can silently share other available hardware resources in the other cores on the same chip. The hardware budget of our method is small, and the implementation is trivial. The initial analysis tells us that it is a promising way to improve sequential program performance in a chip multicore processor.
Starting Page	268
Ending Page	276
File Size	609925
Page Count	9
File Format	PDF
ISBN	9780769536880
DOI	10.1109/ITCS.2009.272
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-25
Publisher Place	Ukraine
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Multicore processing Silent Sharing Sequential Program Execution chip multicore processor Information technology Delay Space heating Computer science Parallel processing Hardware Performance analysis Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The road to parallelism leads through sequential programming.

Boost sequential program performance using a virtual large instruction window on chip multicore processor.

Energy consumption model over parallel programs implemented on multicore architectures

Chameleon: Operating System Support for Dynamic Processors

Chameleon: operating system support for dynamic processors.

Multicore Processing and Efficient On-Chip Caching for H.264 and Future Video Decoders

Efficient threads mapping on multicore architecture

Energy-Efficient Scheduling on Milliclusters with Performance Constraints

Exploring practical benefits of asymmetric multicore processors.

Silent Sharing: An Efficient Mechanism to Fast Sequential Program Execution on Chip Multicore Processor

Similar Documents

The road to parallelism leads through sequential programming.

Boost sequential program performance using a virtual large instruction window on chip multicore processor.

Energy consumption model over parallel programs implemented on multicore architectures

Chameleon: Operating System Support for Dynamic Processors

Chameleon: operating system support for dynamic processors.

Multicore Processing and Efficient On-Chip Caching for H.264 and Future Video Decoders

Efficient threads mapping on multicore architecture

Energy-Efficient Scheduling on Milliclusters with Performance Constraints

Exploring practical benefits of asymmetric multicore processors.

Silent Sharing: An Efficient Mechanism to Fast Sequential Program Execution on Chip Multicore Processor