NDLI: A hierarchical variable-sized block transform coding scheme for coding efficiency improvement on H.264/AVC

Content Provider	IEEE Xplore Digital Library
Author	Bumshik Lee Jaeil Kim Sangsoo Ahn Munchurl Kim Hui Yong Kim Jongho Kim Jin Soo Choi
Copyright Year	2010
Description	Author affiliation: Korea Advanced Institute of Science and Technology (KAIST) (Bumshik Lee; Jaeil Kim; Sangsoo Ahn; Munchurl Kim) \|\| Electronic Telecommunications Research Institute (ETRI) (Hui Yong Kim; Jongho Kim; Jin Soo Choi)
Abstract	In this paper, a rate-distortion optimized variable block transform coding scheme is proposed based on a hierarchical structured transform for macroblock (MB) coding with a set of the order-4 and −8 integer cosine transform (ICT) kernels of H.264/AVC as well as a new order-16 ICT kernel. The set of order-4, −8 and −16 ICT kernels are applied for inter-predictive coding in square (4×4, 8×8 or 16×16) or non-square (16×8 or 8×16) transform for each MB in a hierarchical structured manner. The proposed hierarchical variable-sized block transform scheme using the order-16 ICT kernel achieves significant bitrate reduction up to 15%, compared to the High profile of H.264/AVC. Even if the number of candidates for the transform types increases, the encoding time can be reduced to average 4–6% over the H.264/AVC
Starting Page	522
Ending Page	525
File Size	155460
Page Count	4
File Format	PDF
ISBN	9781424471348
e-ISBN	9781424471355
DOI	10.1109/PCS.2010.5702553
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-08
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Variable Block-size Transform Discrete Cosine Transform Transform coding Automatic voltage control Encoding Discrete cosine transforms H.264/AVC Quadtree Transform Kernel Pixel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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