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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tae Hun Kim Tae Doo Park Gun Yeol Park Hae Chan Kwon Ji Won Jung |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Radio Commun. Eng., Korea Maritime Univ., Busan, South Korea (Tae Hun Kim; Tae Doo Park; Gun Yeol Park; Hae Chan Kwon; Ji Won Jung) |
| Abstract | This paper proposed a new decoder architecture which employs HSS algorithm and simple check node update algorithm. Memory architecture is a major point of in terms of high speed and area of implementation, therefore the efficient memory design to accelerate decoding throughput is studied. In conventional decoder architectures, p- parallelism, dc-serialism, and q-serialism are required. This paper attempted memory division to obtain dc-parallelism and memory sharing to reduce area, 7 times of decoder throughput may be improved compared to conventional one. |
| Starting Page | 430 |
| Ending Page | 434 |
| File Size | 733714 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467359900 |
| ISSN | 21658528 |
| DOI | 10.1109/ICUFN.2013.6614855 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-07-02 |
| Publisher Place | Vietnam |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | dcparallelism High throughput Normalized Min Sum(NMS) Memory architecture LDPC decoding throughput Throughput HSS Decoding Iterative decoding Digital video broadcasting |
| Content Type | Text |
| Resource Type | Article |
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