NDLI: Partial controller retiming in high-level synthesis

Content Provider	IEEE Xplore Digital Library
Author	Sobue, R. Hara-Azumi, Y. Tomiyama, H.
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan (Sobue, R.; Tomiyama, H.) \|\| Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan (Hara-Azumi, Y.)
Abstract	Various optimization techniques of high-level synthesis (HLS) have been studied for improving clock frequency. However, they focus only on the datapath and cannot handle the controller delay even though most critical paths lie across the controller and datapath (i.e., from state registers in the controller to storage units in the datapath) and the controller delay occupies the non-negligible portion of the paths. This paper proposes a novel HLS technique to remove such controller delays. Our method, “Register-Transfer (RT) level register retiming”, is applied to only parts of the control logic, which generate control signals of multiplexers (MUXs) on critical paths, in such a way that generates and stores the signals into registers in the previous cycle. It then lets the MUXs obtain their control signals directly from the registers, leading to reduction in critical path delay. Experiments on several benchmark programs demonstrate that our RT-level retiming can achieve comparable clock improvement while mitigating area overhead, compared with conventional gatelevel retiming.
Starting Page	1
Ending Page	6
File Size	146343
Page Count	6
File Format	PDF
ISBN	9781467364140
e-ISBN	9782953998795
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	multiplexers High-level synthesis Transform coding Logic gates Benchmark testing Hardware register retiming Registers Delays Clocks
Content Type	Text
Resource Type	Article

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