NDLI: Selector design considerations and requirements for 1 SIR RRAM crossbar array

Content Provider	IEEE Xplore Digital Library
Author	Leqi Zhang Cosemans, S. Wouters, D.J. Groeseneken, G. Jurczak, M. Govoreanu, B.
Copyright Year	2014
Description	Author affiliation: imec, Leuven, Belgium (Leqi Zhang; Cosemans, S.; Wouters, D.J.; Groeseneken, G.; Jurczak, M.; Govoreanu, B.)
Abstract	This work investigates the impact of selector characteristics on the overall 1S1R cell performance. Selector requirements are extracted using parameterized characteristics for an 1Mbit array, taking into account the read/write margins and power consumption constraints. Array sizing simulation results show that the voltage operating range of the selector is important. Selectors with large voltage operation range improve full cell non-linearity, but this comes at the cost of reduced 1S1R read window and the need of high voltage during both read and write operations. Using optimized bias scheme enables a larger design margin for the selector compared to the standard 1/2 or 1/3 bias scheme. The use of lower switching current resistive element also enlarges the selector design range, allowing lower non-linearity and voltage operation range. In case a low switching current resistive element is used, it is the read operation that imposes the minimum selector requirements.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	1
Ending Page	4
File Size	1300951
Page Count	4
File Format	PDF
ISBN	9781479935949
e-ISBN	9781479935963
DOI	10.1109/IMW.2014.6849358
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-18
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistance Low voltage Power demand 1S1R Switches RRAM Arrays Leakage currents Mathematical model crossbar array Selector
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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