NDLI: A comparative study of the program efficiency of gate all around SONOS and TANOS flash memory

Content Provider	IEEE Xplore Digital Library
Author	Junghwan Ji Byung-Gook Park Jong Ho Lee Hyungcheol Shin
Copyright Year	2010
Description	Author affiliation: Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, and Computer Science, Seoul National University, San 56-1, Daehak-dong, Gwanak-gu, 151-742, Republic of Korea (Junghwan Ji; Byung-Gook Park; Jong Ho Lee; Hyungcheol Shin)
Abstract	An analytic expression was obtained to examine the dependence of dielectric layers thickness and silicon radius on Vth shift, which is an important characteristic of gate all around SONOS/TANOS memory. As the radius of silicon decreases, the Vth shift decreases because of increasing capacitance in dielectric layers under the condition of same trapped charge density. The Vth shift is almost linearly dependant on bottom oxide thickness and top oxide thickness. The maximum Vth shift of TANOS is lower than that of SONOS because of high dielectric constant of blocking layer in TANOS. On the other hand, the program speed of TANOS is faster than that of SONOS.
Starting Page	1
Ending Page	2
File Size	411657
Page Count	2
File Format	PDF
ISBN	9781424467198
e-ISBN	9781424467211
e-ISBN	9781424476688
DOI	10.1109/IMW.2010.5488407
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-16
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SONOS devices High-K gate dielectrics Computer science Nonvolatile memory Flash memory Voltage Capacitance Silicon Electronic mail Aluminum oxide
Content Type	Text
Resource Type	Article

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