NDLI: An evolutionary algorithm testbed for quick implementation of algorithms in hardware

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An evolutionary algorithm testbed for quick implementation of algorithms in hardware

Content Provider	IEEE Xplore Digital Library
Author	Smilkstein, T. Tati, K.K. Barve, P. Hai, M.L. Sajjapongse, K. Sharma, D.K.
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, University of Missouri, U.S.A. (Smilkstein, T.; Tati, K.K.; Barve, P.; Hai, M.L.; Sajjapongse, K.; Sharma, D.K.)
Abstract	We have developed a general purpose evolutionary algorithm testbed (GPeat) that allows evolutionary algorithm designers to quickly and with minimal hardware knowledge move their algorithms into hardware. A user programs the testbed through a graphical user interface (GUI) that lets the user choose system parameters such as types and combinations of crossovers and mutations, initial population descriptions, fitness function rules, criteria for selection and elitism rates. A variety of sensors or computer connections can be made to the testbed so that both intrinsic and extrinsic runs can be carried out. Outputs of the testbed can likewise be computer or device directed. Use of the GUI requires minimal knowledge of hardware and connecting sensors and output devices to the board requires only the ability to identify basic device characteristics (i.e. voltage or current output, analog or digital output). In this first version, sensor inputs, fitness/chromosome value pairs, generated initial values, selected outputs are dumped to a file on the computer for analysis. New evolutionary algorithm specific hardware structures have also been developed which can provide faster run times than direct FPGA implementations. This tool will allow quick prototyping for those wanting to move their algorithms from the computer to the real world, the option to use the hardware as a debugging tool or as the final embedded, portable evolutionary algorithm hardware system.
Starting Page	51
Ending Page	57
File Size	738727
Page Count	7
File Format	PDF
ISBN	9781424427543
DOI	10.1109/ESDIS.2009.4938999
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis System testing Genetic mutations Evolutionary computation Voltage Sensor phenomena and characterization Hardware Joining processes Biological cells Graphical user interfaces
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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