NDLI: A CMOS image sensor with non-memory capacitor two-step single slope ADC for high frame rate

Content Provider	IEEE Xplore Digital Library
Author	Lee, Junan Lee, Jongyeon Burm, Jinwook
Copyright Year	2015
Description	Author affiliation: Dept. of Electronics Engineering, Sogang University, 121-742, Sinsu-dong, Mapo-gu Seoul, Korea (Lee, Junan; Lee, Jongyeon; Burm, Jinwook)
Abstract	This paper proposes a column-parallel two-step Single-Slope Analog-to-Digital Converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). The total power consumption is 72 mW from supply voltages of 2.8 V(analog) and 1.5 V (digital). The Figure of Merit (FoM) is 2.01 [e-nJ].
Starting Page	333
Ending Page	334
File Size	289210
Page Count	2
File Format	PDF
e-ISBN	9781467393089
DOI	10.1109/ISOCC.2015.7401723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image resolution Radiation detectors Capacitors Column-parallel ADC Random access memory Non-memory capacitor CMOS image sensors Generators Two-step ADC Analog memory Single-slope (SS) ADC
Content Type	Text
Resource Type	Article

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