NDLI: Transistor layout optimization for leakage saving

Content Provider	IEEE Xplore Digital Library
Author	Myunghwan Ryu Yesung Kang Youngmin Kim
Copyright Year	2013
Description	Author affiliation: Ulsan Nat. Inst. of Sci. & Technol., Ulsan, South Korea (Myunghwan Ryu; Yesung Kang; Youngmin Kim)
Abstract	In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased $I_{on}$ with decreased $I_{off}$ because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage).
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	253
Ending Page	254
File Size	93575
Page Count	2
File Format	PDF
ISBN	9781479911424
DOI	10.1109/ISOCC.2013.6864020
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-17
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Shape diffusion rounding Leakage currents Optimization variation static power Layout TCAD Logic gates CMOS integrated circuits Transistors gate biasing leakage
Content Type	Text
Resource Type	Article

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