NDLI: Resolution mosaic-based Smart Camera for video surveillance

Content Provider	IEEE Xplore Digital Library
Author	Salem, M.A.-M. Klaus, K. Winkler, F. Meffert, B.
Copyright Year	2009
Description	Author affiliation: Humboldt-Universitaet zu Berlin, Signal Processing and Pattern Recognition Group, Department of Computer Science, Unter den Linden 6, 10099, Germany (Klaus, K.; Winkler, F.; Meffert, B.) \|\| Ain Shams University, Faculty of Computer and Information Sciences, Abbassia 11566, Cairo, Egypt (Salem, M.A.-M.)
Abstract	Video surveillance is one of the most data intensive applications. A typical video surveillance system consists of one or multiple video cameras, a central storage unit, and a central processing unit. At least two bottlenecks exist: First, the transmission capacity is limited, especially for raw data. Second, the central processing unit has to process the incoming data to give results in real time. Therefore, we propose an FPGA-based embedded camera system which performs all steps of image acquisition, region of interest extraction, generation of a multiresolution image, and image transmission. The proposed pipeline-based architecture allows a real time wavelet-based image segmentation and a detection of moving objects for surveillance purposes. The system is integrated in a single FPGA using external RAM as storage for images and for a Linux operating system which controls the data flow. With the pipeline concept and a Linux device driver it is possible to create a system for streaming the results of an image processing through a GbE interface. A real time processing is achieved. The camera transmits the captured images with 30 $^{Mpixel/s},$ but the system is able to process 100 $^{Mpixel/s}.$
Starting Page	1
Ending Page	7
File Size	761575
Page Count	7
File Format	PDF
ISBN	9781424446209
DOI	10.1109/ICDSC.2009.5289364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-30
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image resolution Image communication 3D Wavelet Transform FPGA Image Segmentation Smart Camera Data mining Image segmentation Linux Multiresolution Smart cameras Object detection Video surveillance Central Processing Unit Image storage
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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