NDLI: Hardware, Design and Implementation Issues on a Fpga-Based Smart Camera

Content Provider	IEEE Xplore Digital Library
Author	Dias, F. Berry, F. Serot, J. Marmoiton, F.
Copyright Year	2007
Description	Author affiliation: Univ. Blaise Pascal, Aubiere (Dias, F.; Berry, F.; Serot, J.; Marmoiton, F.)
Abstract	Processing images to extract useful information in real-time is a complex task, dealing with large amounts of iconic data and requiring intensive computation. Smart cameras use embedded processing to save the host system from the low-level processing load and to reduce communication flows and overheads. Field programmable devices present special interest for smart cameras design: flexibility, reconfigurability and parallel processing skills are some specially important features. In this paper we present a FPGA-based smart camera research platform. The hardware architecture is described, and some design issues are discussed. Our goal is to use the possibility to reconfigure the FPGA device in order to adapt the system architecture to a given application. To that, a design methodology, based on pre-programmed processing elements, is proposed and sketched. Some implementation issues are discussed and a template tracking application is given as example, with its experimental results.
Starting Page	20
Ending Page	26
File Size	5142276
Page Count	7
File Format	PDF
ISBN	9781424413539
DOI	10.1109/ICDSC.2007.4357501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-25
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	design methodology Face recognition Image processing Design methodology reconfigurable architecture Face detection Data mining Smart camera Smart cameras Computer architecture Object detection embedded image processing Hardware Field programmable gate arrays FPGA-based system
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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