NDLI: A novel FPGA implementation of adaptive color image enhancement based on HSV color space

Content Provider	IEEE Xplore Digital Library
Author	Hanumantharaju, M.C. Ravishankar, M. Rameshbabu, D.R. Ramachandran, S.
Copyright Year	2011
Description	Author affiliation: Department of Computer Science & Engineering, Dayananda Sagar College of Engineering, Bangalore, India - 560078 (Rameshbabu, D.R.) \|\| Department of Electronics & Communication Engineering SJB Institute of Technology, Bangalore, India - 560060 (Ramachandran, S.) \|\| Department of Information Science & Engineering (Hanumantharaju, M.C.; Ravishankar, M.)
Abstract	In this paper, a new algorithm and a novel architecture suitable for Field Programmable Gate Array (FPGA) implementation of adaptive color image enhancement based on Hue-Saturation-Value (HSV) color space is presented. The contrast and luminance of the color image is enhanced by using saturation feedback. The saturation component is enhanced by stretching its dynamic range to get rich color display. Hue is preserved in order to avoid color distortion. The adaptive luminance enhancement is achieved by using a simple geometric mean filter since traditional arithmetic mean filter tends to lose image detail such as edges and sharpness when compared to geometric mean filter. An efficient architecture for histogram equalization is also developed in order to evaluate the performance of proposed algorithm. The algorithm is implemented on Xilinx Vertex II XC2V2000–4ff896 FPGA device. The pipelining and parallel processing techniques have been adapted in order to speed up the enhancement process. The experimental results show that the color images enhanced by the proposed algorithm are clearer, vivid and efficient.
Starting Page	160
Ending Page	163
File Size	758912
Page Count	4
File Format	PDF
ISBN	9781424486786
e-ISBN	9781424486793
DOI	10.1109/ICECTECH.2011.5941676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-08
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Histograms Geometric Mean Filter Image color analysis FPGA Color Filtering algorithms Hardware HSV Saturation Feedback Adaptive Color Image Enhancement Field programmable gate arrays Pixel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in