NDLI: Designing floating codes for expected performance

Content Provider	IEEE Xplore Digital Library
Author	Finucane, H. Zhenming Liu Mitzenmacher, M.
Copyright Year	2008
Description	Author affiliation: Sch. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA (Finucane, H.; Zhenming Liu; Mitzenmacher, M.)
Abstract	Floating codes are codes designed to store multiple values in a write asymmetric memory, with applications to flash memory. In this model, a memory consists of a block of n cells, with each cell in one of q states {0,1, . . .,q - 1}. The cells are used to represent k variable values from an lscr-ary alphabet. Cells can move from lower values to higher values easily, but moving any cell from a higher value to a lower value requires first resetting the entire block to an all 0 state. Reset operations are to be avoided; generally a block can only experience a large but finite number of resets before wearing out entirely. A code here corresponds to mapping from cell states to variable values, and a transition function that gives how to rewrite cell states when a variable is changed. Previous work has focused on the developing codes that maximize the worst-case number of variable changes, or equivalently cell rewrites, that can be experienced before resetting. In this paper, we introduce the problem of maximizing the expected number of variable changes before resetting, given an underlying Markov chain that models variable changes. We demonstrate that codes designed for expected performance can differ substantially from optimal worst-case codes, and suggest constructions for some simple cases.
Starting Page	1389
Ending Page	1396
File Size	135780
Page Count	8
File Format	PDF
ISBN	9781424429257
DOI	10.1109/ALLERTON.2008.4797723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design engineering Codes Nonvolatile memory Flash memory Performance analysis Electrons Testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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