NDLI: FFT-based sonar array beamforming without corner turning

Content Provider	IEEE Xplore Digital Library
Author	Barhen, J. Humble, T. Traweek, M.
Copyright Year	2008
Description	Author affiliation: Oak Ridge Nat. Lab., Oak Ridge, TN (Barhen, J.; Humble, T.) \|\| Office of Naval Res., Arlington, VA (Traweek, M.)
Abstract	The concept of ldquocorner turningrdquo has been, for many decades, at the heart of array beamforming via Fourier transforms. As widely reported in the open literature (both for sonars and radars), corner turning operations in the computational sequence Lttemporal Fourier transforms rarr data cube corner turning rarr spatial Fourier transformsGt, constitute a major obstacle to achieve high-performance and lower power dissipation (by reducing the number memory accesses). To date, leading industry providers still include explicit corner turning stages in their computational flow architectures for multidimensional array processing. The emergence of ultra-low power multicore processors opens unprecedented opportunities for implementing sophisticated signal processing algorithms faster and within a much lower energy budget. In that context, the primary innovation reported in this paper addresses the development of a computational scheme that avoids altogether the corner turning stage. We discuss its implementation on an IBM Cell multicore processor (Sony PS3) and provide preliminary timing results.
Starting Page	1
Ending Page	6
File Size	745422
Page Count	6
File Format	PDF
ISBN	9781424428151
DOI	10.1109/PASSIVE.2008.4786980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heart Fourier transforms Array signal processing Multicore processing Sonar Radar Computer architecture Turning Computer industry Power dissipation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Elimination of corner‐turning in FFT‐based sonar array beamforming

Fast adaptive Bayesian beamforming using the FFT

FFT-Based Analog Beamforming Processor

A 32 point monolithic FFT processor chip

A pipelined, high-precision FFT architecture

An event controlled reconfigurable multi-chip FFT

Frequency broadband signal MVDR adaptive beamforming method and application

A reconfigurable and high precision VLSI architecture for Fast Fourier Transform

A fast Fourier transform (FFT) based sonar signal processor

FFT-based sonar array beamforming without corner turning

Similar Documents

Elimination of corner‐turning in FFT‐based sonar array beamforming

Fast adaptive Bayesian beamforming using the FFT

FFT-Based Analog Beamforming Processor

A 32 point monolithic FFT processor chip

A pipelined, high-precision FFT architecture

An event controlled reconfigurable multi-chip FFT

Frequency broadband signal MVDR adaptive beamforming method and application

A reconfigurable and high precision VLSI architecture for Fast Fourier Transform

A fast Fourier transform (FFT) based sonar signal processor

FFT-based sonar array beamforming without corner turning