NDLI: Instruction prefetching using Basicblock prediction

Content Provider	IEEE Xplore Digital Library
Author	Shyamala, K. Ravibabu, P. Lokhande, S.K. Reddy, R. Das, S.
Copyright Year	2008
Description	Author affiliation: Univ. Coll. of Eng., Osmania Univ., Hyderabad (Shyamala, K.; Lokhande, S.K.; Reddy, R.; Das, S.) \|\| Univ. of Hyderabad, Hyderabad (Ravibabu, P.)
Abstract	Memory latency is a significant bottleneck in modern computer architectures, especially for commercial and multimedia applications. Instruction cache misses can severely limit the performance, due to advent of superscalar processors and multicore systems. Prefetching is one of the promising method to bridge the performance gap between CPU and DRAM speed. Although Instruction prefetching is a promising technique to hide the memory latency, they fail to issue prefetches early enough for modern superscalar processors. To overcome these limitations, we propose a new instruction prefetching technique called Basicblock Instruction Prefetching that employs a prefetch engine which issues prefetch instructions to achieve useful and early prefetches far enough in advance. Our prefetching design results in good coverage, is accurate, and produces timely results that can be effectively used by the processor. Performance evaluation is carried out through cycle-accurate trace-driven simulation. The experimental results show that the proposed scheme is successful in 80% accurate prediction and achieves better timeliness.
Starting Page	1
Ending Page	4
File Size	946122
Page Count	4
File Format	PDF
ISBN	9781424423156
DOI	10.1109/ICED.2008.4786750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-01
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Portable Instruction Set Architecture (PISA) Multicore processing Prefetching Basicblock Educational institutions Application software Delay Engines Bridges Simplescalar Computer architecture Hardware Performance loss Basicblock Instruction Prefetching (BIP) Prefetch
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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