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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhou Yi Zhou Zhonghua Hou Ligang Wu Wuchen |
| Copyright Year | 2010 |
| Description | Author affiliation: VLSI & System Lab of Beijing University of technology, China (Zhou Yi; Zhou Zhonghua; Hou Ligang; Wu Wuchen) |
| Abstract | Serial communication system has been widely used in data communications and control system because of less hardware resources, anti-jamming ability, and easy to implement features. A FPGA-based high performance Serial communication system interface module which includes full functions of UART16550 is designed and optimized based on the communication protocol and working principles in this paper. Various technologies are adopted during the design and optimization procedure, such as the three always block coding style, EDA optimization, circuit optimization, and so on. The frequency of the optimized design is up to 166MHz, and the power consumptionis reduced to 0.147W by 63.9%. The test data at typical baud-rate of 115200 and the analyzed result by using Matlab are presented. The test results indicate that the optimized design can be communicated correctly and steadily. |
| File Size | 287788 |
| File Format | |
| ISBN | 9781424463473 |
| e-ISBN | 9781424463497 |
| DOI | 10.1109/ICCET.2010.5485403 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-04-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | STA Protocols Electronic design automation and methodology Circuit optimization FPGA Communication system control Serial communication Control systems Circuit testing Design optimization Matlab analyse Timing Optimization Hardware Data communication Block codes |
| Content Type | Text |
| Resource Type | Article |
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