NDLI: FPGA Implementation of the Ternary Pulse Compression Sequences with Good Discrimination Factor Values

Content Provider	IEEE Xplore Digital Library
Author	Balaji, N. Rao, K.S. Rao, M.S.
Copyright Year	2009
Abstract	Ternary codes have been widely used in radar and communication areas, but the synthesis of ternary codes with good discrimination factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design Ternary Pulse compression sequences with good discrimination factor. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability. The implemented architecture overcomes the drawbacks of non guaranteed convergence of the earlier optimization algorithms.
Starting Page	353
Ending Page	357
File Size	267970
Page Count	5
File Format	PDF
ISBN	9781424433346
DOI	10.1109/ICCET.2009.222
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-22
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse compression methods Very large scale integration VLSI architecture Radar applications Pulse compression Convergence Genetic algorithms Spread spectrum radar Pulse generation Sidelobe energy FPGA. Signal processing algorithms Autocorrelation Ternary sequence Merit Factor Field programmable gate arrays
Content Type	Text
Resource Type	Article

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