NDLI: Efficient task scheduling algorithm for triplet architecture TriBA

Content Provider	IEEE Xplore Digital Library
Author	Haroon-Ur-Rashid Shi Feng Kamran, M.
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, University of Engineering and Technology, Lahore, Pakistan (Kamran, M.) \|\| Department of Computer Science and Technology, Beijing Institute of Technology (BIT), China (Haroon-Ur-Rashid; Shi Feng)
Abstract	This paper proposes an algorithmic approach to task scheduling for new idea in high performance architectures, TriBA. TriBA is considered to be a high performance, distributed parallel computing architecture. The root of “triplet based architecture” is based on the concept that “Complex problems can be decomposed to three relatively independent sub-problems, which are data Processing, data Management and data Communication”. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors. TriBA is a real scalable architecture, featuring fractal nature for computers. TriBA is a new solution for computer architecture, which is suitable for sophisticated embedded applications with multiple concurrent processing centers. In parallel or distributed environment an efficient assignement of tasks to the processing elements is imperative to achieve fast job turnaround time. Moreover, the sojourn time experienced by each individual job should be minimized. The arriving jobs are comprised of parallel applications, each consisting of multiple-independent tasks that must be instantaneously assigned to processor queues, as they arrive. The processors independently and concurrently service these tasks. Our algorithm approach achieves optimality in task scheduling by assigning consecutive tasks to a triplet of processors exploiting locality in tasks. The key scheduling issues is, when some queue backlogs are small, an incoming job should first spread its tasks to those lightly loaded queues in order to take advantage of the parallel processing gain. Finally, task scheduling has been analyzed as a performance metric using relation between speedup, number of processors and communication cost.
Starting Page	149
Ending Page	154
File Size	1249906
Page Count	6
File Format	PDF
ISBN	9781424486502
e-ISBN	9789698741075
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-19
Publisher Place	Pakistan
Access Restriction	Subscribed
Rights Holder	CESAT
Subject Keyword	Program processors Multiprocessor architecture mapping hierarchical interconnection Von Neumann architecture Computer architecture Sierpinski gasket task scheduling complex embedded applications parallel processing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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