NDLI: Job Phasing Aware Preemption Deferral

Content Provider	IEEE Xplore Digital Library
Author	Marinho, J. Petters, S.M.
Copyright Year	2011
Abstract	Preemptions account for a non-negligible overhead during system execution. There has been substantial amount of research on estimating the delay incurred due to the loss of working sets in the processor state (caches, registers, TLBs) and some on avoiding preemptions, or limiting the preemption cost. We present an algorithm to reduce preemptions by further delaying the start of execution of high priority tasks in fixed priority scheduling. Our approaches take advantage of the floating non-preemptive regions model and exploit the fact that, during the schedule, the relative task phasing will differ from the worst-case scenario in terms of admissible preemption deferral. Furtehrmore, approximations to reduce the complexity of the proposed approach are presented. Substantial set of experiments demonstrate that the approach and approximations improve over existing work, in particular for the case of high utilisation systems, where savings of up to 22% on the number of preemption are attained.
Starting Page	128
Ending Page	135
File Size	496166
Page Count	8
File Format	PDF
ISBN	9781457718229
DOI	10.1109/EUC.2011.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-24
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Schedules Processor scheduling Complexity theory Mathematical model Approximation methods Equations Delay
Content Type	Text
Resource Type	Article

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