NDLI: Zero-Hardened SRAM Cells to Improve Soft Error Tolerance in FPGA

Content Provider	IEEE Xplore Digital Library
Author	Si Miao Peng Ou Xuegong Zhou Lingli Wang
Copyright Year	2008
Description	Author affiliation: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai (Si Miao; Peng Ou; Xuegong Zhou; Lingli Wang)
Abstract	Soft errors due to charged particle strikes at the sensitive cell nodes could modify the functionality of the design by changing the configuration bits of an SRAM based FPGA. However, with the development of very-deep-sub-micron (VDSM) or even the nano-technologies, aggressive device size has impacted severely the soft error rate of integrated circuits. In this paper, three new SRAM cell designs are proposed which mainly aim at reducing the soft error rate in FPGA. We verify the soft error tolerance and the power dissipation of these three designs using HSPICE simulation with Berkeley Predictive Technology Model (PTM) of the 65 nm, 1.0 V technology. The simulation results of our three designs are compared with that of standard 6-transistor SRAM cell and an existing increased soft error tolerance cell - ASRAM0. Comparison result shows that our new cells, especially the 0-hardened SRAM cell, have triple the critical charge of the standard 6-transistor SRAM cell, when the cell is storing 0.
Starting Page	278
Ending Page	282
File Size	393437
Page Count	5
File Format	PDF
ISBN	9780769534978
DOI	10.1109/IITA.2008.336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit technology Error analysis FPGA Random access memory Predictive models Routing Integrated circuit reliability SRAM Soft error Voltage Computer errors Capacitance Field programmable gate arrays
Content Type	Text
Resource Type	Article

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