NDLI: FPGA-based embedded speed limit enforcement system on freeway

Content Provider	IEEE Xplore Digital Library
Author	Fu Jian-qun Shi Zhong-ke
Copyright Year	2010
Description	Author affiliation: College of Automation, Northwestern Polytechnical University, Xi'an 710072, China (Fu Jian-qun; Shi Zhong-ke)
Abstract	Speeding is recognized as a major contributing factor in traffic accidents on freeway. In order to reduce speed-related accidents, accurate real-time speed limit enforcement system is very critical to freeway. This paper presents an automatic speed limit enforcement system on freeway based on cameras and the Field Programmable Gate Array (FPGA) implementation to achieve this objective. Taking the advantage of the powerful parallel processing architecture of FPGA, this FPGA-based system can provide a real-time, low-cost, high-performance hardware platform for multi-channel video system to achieve real-time image processing. Once the speeding vehicle is detected, the system will immediately record the panoramic view of the vehicle passing and basic characteristics of the vehicle, shoot of the vehicle number plate, the vehicle speed, passing time, etc., and send this information to the monitoring center by the wireless modem through the serial interface and the GPRS network. The experiments indicated that the speed limit enforcement system can detect the vehicle speed accurately and provide the necessary proof for the police to enact punishment.
File Size	1240491
File Format	PDF
ISBN	9781424465392
ISSN	21547491
e-ISBN	9781424465422
DOI	10.1109/ICACTE.2010.5579175
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Economics freeway Law FPGA Random access memory Variable speed drives Logic gates speed limit enforcement system intelligent transportation P-tile threshold segmentation method Monitoring
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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