NDLI: The design and implementation of General Marking System for Circuit-based Virtual Experiment

Content Provider	IEEE Xplore Digital Library
Author	Zhenyu Wang Fuan Wen Meisong Chen YanLian Sun
Copyright Year	2010
Description	Author affiliation: Institute of Cyber Education Technology, Beijing University of Posts and Telecommunications, 100876, China (Zhenyu Wang; Fuan Wen; Meisong Chen; YanLian Sun)
Abstract	Due to its outstanding contributions in overcoming the device limitations in traditional experiment process, as well as improving the practice and operation capacity of students, virtual experiment has become an indispensable part of E-learning, and has been widely applied during recent years. As one of the supportive components of virtual experiment, marking system provides an open platform for virtual experiment results evaluation, which could greatly improve the efficiency in teaching and learning process by replacing manually marking with automatic operations. In this paper, features of Circuit-based Virtual Experiment (CVE) are taken into analysis, and a General Marking System (GMS) model is proposed accordingly. Based on such model, customized marking rules and facts are extracted from experimental result scripts, and then delivered into the rule engine for further process. Responses of matched rules and facts are collected and the final evaluations of such experiment will be formed. Examples of circuit analysis virtual experiment are presented to illustrate the enhancement of generality, reliability and flexibility in virtual experiment progress.
File Size	570615
File Format	PDF
ISBN	9781424465392
ISSN	21547491
e-ISBN	9781424465422
DOI	10.1109/ICACTE.2010.5579438
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors General Marking System XML Manuals Virtual Experiment Lead Telecommunication network reliability Integrated circuit reliability Rule Engine Circuit-based Virtual Experiment
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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