NDLI: Fast and accurate technique to decompose jitter for very long pattern length waveform

Content Provider	IEEE Xplore Digital Library
Author	Kho, Joseph Ling, Tan Yih
Copyright Year	2014
Description	Author affiliation: PEIP- High Speed Validation, Altera Corporation (M) Sdn. Bhd, Plot 6, Bayan Lepas, 11900 Penang, Malaysia (Kho, Joseph; Ling, Tan Yih)
Abstract	Protocols such as CEI, 10G Ethernet and PCIe Gen3 are requiring very long pattern length stress signals such as PRBS-23 and PRBS-31 to claim compliance and ensure robustness. Unfortunately, there is equipment limitation to directly measure very long pattern signals especially on oscilloscopes due to memory size and signal processing power. Thus, new jitter decomposition algorithms are introduced to measure these long stress patterns through behavioral modeling [1–3]. However, there are accuracy concerns with these new measurement methodologies because of incidences of false results when users attempt to qualify or debug a circuit. This paper will explore the limitations of different jitter decomposition algorithms from major equipment vendors in the industry when measuring very long pattern length waveforms. We will also provide the measurement method and calculations required to obtain the correct jitter decomposition. Correlation of the calculated number against direct measurement using bit error rate tester (BERT) is also done to prove the hypothesis and validate accuracy of the methodology. The findings in this paper are very beneficial in assisting the industry to perform accurate jitter measurements with shorter test time to achieve robust designs as well as prevent precious resources from being spent on investigating false failures. The findings also allow companies to show that their products are tested under stringent conditions that satisfy customer requirements.
Starting Page	93
Ending Page	96
File Size	551906
Page Count	4
File Format	PDF
ISBN	9781479962570
DOI	10.1109/EDAPS.2014.7030815
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-14
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Repeating Pattern Bit error rate Noise PMA Oscilloscopes Jitter Signal Integrity Transceiver Arbitrary Pattern Q measurement Accuracy PRBS Real-time systems Oscilloscope
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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